Japanese Patent Application No. 2001-393630, filed on Dec. 26, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a ferroelectric memory device. More particularly, the present invention relates to a simple matrix type ferroelectric memory device.
A simple matrix type ferroelectric memory device using only ferroelectric capacitors instead of cell transistors has a very simple structure and enables a higher degree of integration. Therefore, development of such a memory device has been expected.
Japanese Patent Application Laid-open No. 9-116107 discloses technology relating to a simple matrix type ferroelectric memory device and an operation method therefor.
A method of writing and reading data disclosed in Japanese Patent Application Laid-open No. 9-116107 is described below. FIG. 9 is a view showing a memory cell array of a ferroelectric memory device.
The method of writing data is described below. FIG. 10 is a timing chart in the case of writing data xe2x80x9c1xe2x80x9d into a ferroelectric capacitor Cm,N and writing data xe2x80x9c0xe2x80x9d into Cm, N+1. In the technology according to Japanese Patent Application Laid-open No. 9-116107, the data xe2x80x9c1xe2x80x9d is written into a memory cell by applying a voltage in a direction so that the potential of a selected sub-bit line is higher than the potential of a selected word line. The data xe2x80x9c0xe2x80x9d is written into the memory cell by applying a voltage in a direction so that the potential of the selected sub-bit line is lower than the potential of the selected word line.
Main bit lines MBLN and MBLN+1 are set to a ground voltage (0 V) at a time t1. At the same time, a selection gate line SL is set to 5 V from 0 V, a selected word line WLm is set to a power supply voltage VCC (3.3 V), and all non-selected word lines WL1 to WLm are set to the ground voltage (0 V). This causes the contents of the ferroelectric capacitors Cm,N and Cm,N+1 to be erased (data xe2x80x9c0xe2x80x9d is written).
At a time t2, the selection gate line SL and the selected word line WLm are set to the ground voltage (0 V), the main bit line MBLN is set to the power supply voltage VCC (3.3 V), and the main bit line MBLN+1 is set to (⅓) VCC (1.1 V).
At a time t3, the selection gate line SL is set to 5 V, the selected word line WLm is set to the ground voltage (0 V), and the non-selected word lines WL1 to WLM are set to (⅔) VCC (2.2 V). This causes the data xe2x80x9c1xe2x80x9d to be written into the ferroelectric capacitor Cm,N.
At a time t4, the main bit lines MBLN and MBLN+1 are set to (⅓) VCC (1.1 V), and the selection gate line SL and the word lines WL1 to WLM are set to the ground voltage (0 V), whereby the write operation is completed.
The method of reading data is described below. FIG. 11 is a timing chart in the case of reading the data xe2x80x9c1xe2x80x9d stored in the memory cell Cm,N and reading the data xe2x80x9c0xe2x80x9d stored in the memory cell Cm,N+1, and rewriting the data xe2x80x9c1xe2x80x9d into the memory cell Cm,N and rewriting the data xe2x80x9c0xe2x80x9d into Cm,N+1.
At the time t1, a precharge signal xcfx86PC is set to the power supply voltage VCC (3.3 V), and a column select signal xcfx86 is set to 5 V. This causes the main bit lines MBLN and MBLN+1 to be precharged to a precharge voltage VPC (0 V) before time t2. The main bit lines MBLN and MBLN+1 are respectively connected to nodes VN and VN+1 of sense amplifiers.
At the time t2, the precharge signal xcfx86PC is dropped to 0 V, thereby causing the main bit lines MBLN and MBLN+1 to be in a floating state. The selection gate line SL is set to 5 V from 0 V, and the selected word line WLm is set to the power supply voltage VCC (3.3 V) from 0 V. This causes the ferroelectric capacitors Cm,N and Cm,N+1 to be in a polarization state in which the data xe2x80x9c0xe2x80x9d is written.
At the time t3, the selection gate line SL and the selected word line WLm are set to 0 V. At the time t4, a sense enable signal xcfx86SE is set to the power supply voltage VCC (3.3 V). This causes sense amplifiers SAN and SAN+1 to be activated. As a result, the data xe2x80x9c1xe2x80x9d is latched by the sense amplifier SAN before a time t5, whereby the potential of the main bit line MBLN is set to the power supply voltage VCC (3.3 V). The data xe2x80x9c0xe2x80x9d is latched by the sense amplifier SAN+1, whereby the potential of the main bit line MBLN+1 is set to the ground voltage (0 V). The read operation is performed in this manner.
Since steps after the time t5 are rewriting steps, description thereof is omitted.
The present invention may provide a ferroelectric memory device with improved operability.
A ferroelectric memory device according to the present invention comprises:
a memory cell array, in which memory cells are arranged, in a matrix, which comprises first signal electrodes, second signal electrodes arranged in a direction which intersects with the first signal electrodes, and a ferroelectric layer disposed at least in intersecting regions in which the first signal electrodes intersect with the second signal electrodes,
wherein, provided that the maximum absolute value of a voltage applied between one of the first signal electrodes and one of the second signal electrodes is Vs, a polarization value P of a ferroelectric capacitor comprising one of the first signal electrodes, one of the second signal electrodes, and the ferroelectric layer is within the range of:
0.1P(+Vs) less than P(xe2x88x92⅓Vs) 
when the applied voltage is changed from +Vs to xe2x88x92⅓Vs, and
0.1P(xe2x88x92Vs) greater than P(+⅓Vs) 
when the applied voltage is changed from xe2x88x92Vs to +⅓Vs.
The polarization P(+Vs) is positive when the applied voltage is +Vs, and the polarization P(xe2x88x92Vs) is negative when the applied voltage is xe2x88x92Vs.
The difference between the polarization corresponding to the data xe2x80x9c0xe2x80x9d and the polarization corresponding to the data xe2x80x9c1xe2x80x9d can be increased if the polarization of the ferroelectric capacitor satisfies the above conditions. As a result, the ferroelectric memory device can be operated reliably. Specifically, operability of the ferroelectric memory device can be improved.
The ferroelectric memory device of the present invention may have at least any of the following features.
(a) The ferroelectric layer may comprise a compound containing at least Sr, Bi, Nb, and O as constituent elements.
In this case, the compound may have the formula:
SrBixNbyOz 
wherein x may be 1.5 to 2.5, y may be 1.5 to 2.5, and z may be 7 to 11.
In this case, the compound may have the formula:
SrBix(TawNb1xe2x88x92w)yOz 
wherein x may be 1.5 to 2.5, y may be 1.5 to 2.5, z may be 7 to 11, and w may be 0 to 0.9.
(b) The ferroelectric layer may comprise a compound without 90xc2x0 domain.
In this case, the ferroelectric layer may comprise a compound having a tungsten bronze type crystal structure.
In this case, the ferroelectric layer formed using the compound may have the strongest peak of an XRD diffraction line determined using a wide-angle method at the (001) plane.
(c) The ferroelectric layer may comprise a compound containing at least Pb, Ti, and O as constituent elements.
In this case, the ferroelectric layer may comprise a single phase compound.
(d) The ferroelectric layer may comprise a compound containing at least Pb, Ti, Zr, and O as constituent elements.
In this case, the compound may have the formula:
Pbx (Zr1xe2x88x92yTiy)Oz 
wherein x may be 0.9 to 1.3, y may be 0.6 to 1.0, and z may be 2.8 to 3.4.
In this case, the crystal structure of the compound may belong to a tetragonal system.
The ferroelectric layer formed using the compound may have the strongest peak of an XRD diffraction line determined using a wide-angle method at the (001) plane.
(e) Information may be written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in one of the memory cells, and
an absolute value of the write voltage may be less than an absolute value of a saturation voltage at which the remanent polarization of the ferroelectric capacitor is saturated.
The difference between switching polarization and non-switching polarization can be increased by setting the absolute value of the write voltage less than the absolute value of the saturation voltage, in comparison with the case of setting the write voltage the same as the saturation voltage. Therefore, the difference in bit line potential between reading of first data and reading of second data can be increased, whereby malfunctions can be decreased.
The difference between the polarization corresponding to the data xe2x80x9c0xe2x80x9d and the polarization corresponding to the data xe2x80x9c1xe2x80x9d can be further increased for reasons described later, whereby the ferroelectric memory device can be operated more reliably.
In this case, information may be read from a selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in one of the memory cells, and
an absolute value of the read voltage may be less than an absolute value of a saturation voltage.
The absolute value of the write voltage may be the same as the absolute value of the read voltage.
In this case, while information is read from the selected memory cell, part of the information may be simultaneously written into the memory cell.
(f) Information may be written into a selected memory cell by applying a write voltage between one of the first signal electrodes and one of the second signal electrodes in one of the memory cells,
information may be read from a selected memory cell by applying a read voltage between one of the first signal electrodes and one of the second signal electrodes in one of the memory cells, and
provided that the write voltage is xc2x1Vs and the read voltage is one of +Vs and xe2x88x92Vs,
|Vs| may be less than an absolute value of a saturation voltage at which the remanent polarization of the ferroelectric capacitor is saturated.
(g) With regard to the polarization P of the ferroelectric capacitor,
P(0V)/P(Vs) may be greater than 0.6, when the applied voltage is changed from +Vs to xe2x88x92⅓Vs, and
P(0V)/P(xe2x88x92Vs) may be greater than 0.6, when the applied voltage is changed from xe2x88x92Vs to +⅓Vs.
This enables the difference between the polarization corresponding to the data xe2x80x9c0xe2x80x9d and the polarization corresponding to the data xe2x80x9c1xe2x80x9d to be further increased for reasons described later. As a result, the ferroelectric memory device can be operated more reliably.
(h) The memory cell array may be integrated on a single substrate together with a peripheral circuit.
In this case, the ferroelectric memory device may further comprise a peripheral circuit section which selectively writes information into or reads information from the memory cells,
wherein the memory cell array and the peripheral circuit section may be disposed in different layers.
This increases degrees of freedom relating to the formation position of the memory cell array and the peripheral circuit section.
At least interconnecting lines in the peripheral circuit section may be formed of Cu or an alloy containing Cu as an essential component.